EPM7256AETC100-10N

high-density, high performance, CMOS technology

Rated 5 Rating 5 | reviews | Write a review

Price:: US $4.00~4.50 / piece [Get Latest Price]

Reference price:

Qty (lots)	Price/lot
	US $4.00~4.50

PartNumber:: EPM7256AETC100-10N

Brand:: Altera Corporation - ALTR | Pack: TQFP | D/C: 10+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

Quantity:: piece

Total Price:: US $0

Place Order via Escrow Service

Sold By

Mr. Jason's store

(China (Mainland))

add to my favourite

100% Positive feedback

Detailed seller ratings

Visit Store

Contact Now

Esrcow Service

Place orders confidently and securely via it

Safe payments
Quick and easy transactions
Free service charges

Learn More >>

Previous Next

Products Upload time: 2011-05-11

From Other Seller

Part Number:EPM7256AETC100-10N
US $4.00 - 4.50
A50L-0001-0175

US $100.00 - 100.00 / Piece
(0) Remove
2DI240A-055

US $70.00 - 100.00 / Piece
(0) Remove
Quantity:

piece

Product Summary

The EPM7256AETC100-10N is a high-density, high performance device based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, it operates with a 3.3-V supply voltage and provides 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz.

Parametrics

Absolute maximum ratings: (1)Supply voltage: –0.5 to 4.6 V With respect to ground; (2)DC input voltage: –2.0 to 5.75 V; (3)DC output current, per pin: –25 to 25 mA; (4)Storage temperature: –65 to 150 ℃; (5)Ambient temperature: –65 to 135 ℃; (6)Junction temperature: 135 ℃ at BGA, FineLine BGA, PQFP, and TQFP packages, under bias.

Features

Features: (1)High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAXR) architecture; (2)3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability: MAX 7000AE device in-system programmability (ISP) circuitry compliant with IEEE Std. 1532, EPM7128A and EPM7256A device ISP circuitry compatible with IEEE Std. 1532; (3)Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1; (4)Supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71.